Qualcomm Chip Package Interaction (CPI) and Bumping Process Engineer (Senior to Staff level) in Taiwan
Chip Package Interaction (CPI) and Bumping Process Engineer (Senior to Staff level)
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Manufacturing/Quality/Other
The CPI and bump process engineer will be a key member of chip package interaction (CPI) and bumping team responsible for new product introduction (NPI) and high volume production (HVM) support across various silicon technology nodes, foundries, bumping lines and assembly houses for both 300 mm and 200 mm wafers.
The job includes product and test vehicle passivation, redistribution layer (RDL) and bump mask tape out and process set up; product NPI characterization and ramp up data collection; metrology matching and machine fan out; continuous process improvement, HVM issue containment, root cause and resolution.
The candidate is expected to interact closely with foundry backend interconnect, passivation and bumping teams, OSATs bumping and assembly teams, and internal package design and process, quality, test and product development teams to deliver best-in-class design for manufacturability (DFM) on silicon and package interconnect, bump technology, NPI and production execution for Qualcomms products.
Fundamental understanding of silicon backend interconnect, passivation, RDL, bump, packaging, material and equipment.
Strong technical skills in process, material and equipment characterization, failure analysis and FMEA.
Strong technical skills in DOE design and statistical data analysis.
Working knowledge of silicon mask design and tape out, and package layout.
Minimum of 5 years of hands on working experience on silicon interconnect process, bumping and / or RDL process, new production line installation, qualification and production.
Good analytical and project management skills.
Excellent verbal and written communication skills.
Highly motivated and committed to success of the individual and the team.
Able to work flexible hours.
Occasional domestic/international travels needed.
Experienced with interfacing with foundries, bumping lines and assembly house.
Hands-on experience in leading projects and OSATs management in silicon interconnect, bumping, packaging for advanced technologies.
Additional experience in flip chip package, wafer level package, fan out package and module is a plus.
M.S. or Ph.D. Materials Science, Mechanical Engineering, Chemical Engineering or equivalent.
Minimum 10 years related experience for B.S. candidate.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.