Qualcomm Mixed Signal Layout Designer in Shanghai, China

Job Description:

Job Id T1959076

Job Title Mixed Signal Layout Designer

Company-Division Qualcomm Atheros Inc

Qualcomm Atheros at http://www.qualcomm.com/about/businesses/qca

Job Area Engineering - Hardware

Location China - Shanghai

Overview Job Function

  • Depending on experience and ability the Custom Analog Layout Designer will fulfill one or more functions of increasing responsibility:

  • The analog layout designer works closely with the engineering team to implement custom device level mask designs using Cadence and Mentor tools in a version controlled design environment.

  • The analog layout lead at block level designs, reviews, verifies and releases IPs to internal chip projects, often overlapping responsibility as a direct layout contributor.

  • The chip layout lead will plan and integrate a top level chip product, often overlapping responsibility as a block lead.


  • Create, review, verify and deliver high quality layout that conforms to all design requirements.

  • Provide and maintain accurate schedule estimates

  • Meet project milestone deadlines

  • Independently debug complex design and PDK issues

  • Drive and assist in project planning and design kit/methodology improvements



  • Outstanding English written and verbal communication

  • 5+ years' experience in analog/mixed-signal layout

  • Custom layout experience must include circuits such as ADC, DAC, and class D amplifier,PLL,RX,TX, high speed Serdes layout experience is preferred.

  • Full familiarity with Cadence Virtuoso tool suite

  • Full understanding of hierarchical planning (top down and bottom up) and integration

  • Experience including one or more process nodes: 0.18um, 65nm, 40nm, 28nm

  • Strong verification and debugging skills

  • Excellent communication skills and teamwork

  • Proficiency with design management tools


  • Experience leading a team of layout designers

  • Chip level management from project inception through tape out

  • Proficiency with Virtuoso XL schematic driven layout design flow and tools

  • Proficiency with Virtuoso IC61 product generation

  • Proficiency with Synchronicity version control system

  • Proficiency with Mentor Graphics Calibre and RVE debugging

Education Requirements Required: Bachelor/Master degree in Semiconductor, Electronics Engineering

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.