Qualcomm Static Timing Analysis (STA) Physical Design Engineer in Santa Clara, California
Static Timing Analysis (STA) Physical Design Engineer
Qualcomm Technologies, Inc.
Corporate Research & Development at http://www.qualcomm.com/about/research
Engineering - Hardware
California - Santa Clara
The candidate will work with RTL designers and backend engineers to write/review timing constraints, analyze timing, generate timing ECOs to close design timing. The candidate will be responsible for closing timing on block/top level designs, working with RTL designers, PD engineers and SoC timing teams.
10+ years of experience in the following areas are required:
Full-chip Static Timing Analysis, timing constraints generation and debug, timing margins and appropriate I/O budgeting, and timing convergence of large scaled SoCs required
Physical design aspect of timing closure and closing timing by improving placement, routing, cell sizing, buffering, logic optimization, etc. needed
Analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required
Process variation effects and modeling techniques
Scripting language, such as, Perl, Tcl, Unix Shell
The following skills are preferred:
Statistical timing analysis
Methodology or flow development/automation
Good verbal and written communication skills
Ability to work in a team environment
Organized and motivated
Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.