Qualcomm Digital Design Verification Engineer - Memory Controller in Santa Clara, California
Digital Design Verification Engineer - Memory Controller
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
California - Santa Clara
The QCT Memory Controller Design Team is looking for entry level and experienced ASIC Verification Engineers for the next generation high speed DDR Controllers. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
The responsibility of the position involves comprehensive pre-silicon test planning of the DDR subsystem including the memory controler, scalabe and re-usable testbench development using the advanced verification methodology such as systemVerilog-OVM or systemVerilog-UVM, System Verilog Assertion development, functional coverage development and assertion based formal verification (property checking). Candidate will be working with the digital design team, pre-silicon functional verification team and SoC integration team to successfully deploy multi-protocol bus interconnect into complex SoC.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
5 to 12 years of digital design verification experience:
Hardware Verification Language : System Verilog, System Verilog Assertions (SVA)
Verification methodology such as OVM or UVM.Experience and knowledge of memory controller for LP3/LP4 device, testplanning and testbench development skills
Verilog RTL language
Strong fundamentals of Object Oriented Programming (OOP)
Exposure to RTL Design Verification flows is a plus
Required: Bachelor's, Computer Engineering and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.