Qualcomm Staff Eng. - Digital Design: DDR PHY in San Diego, California

Job Description:

Job Id

E1966681

Job Title

Staff Eng. - Digital Design: DDR PHY

Post Date

09/12/2018

Company


Division

Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware

Location

California - San Diego

Job Overview

The Digital Design Engineer will be responsible for designing and implementing DDR PHY IP within Qualcomms Central Engineering organization. You will work closely with architecture, verification, timing and physical design engineers to design and implement control and datapath blocks for DDR PHY interface to LPDDR4 and LPDDR5 DRAMs.

Ideal candidate will have experience on high speed, low power digital logic design with hands on experience on ASIC front end implementation tool flows and silicon bring up. Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, design for test (DFT) flows for stuck and TDF modes, gate level simulation bring up and debug. Position requires working closely with cross functional teams in high paced and dynamic environment to enable all phases of implementation and Si bring up. Prior experience with high speed parallel physical interfaces designs and low power DDR protocols is a plus.

Excellent communication skills including documentation and the ability to work across multiple teams in multiple locations

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications

  • Bachelor's degree in Science, Engineering, or related field.

  • 5+ years ASIC design, verification, or related work experience.

Preferred Qualifications

BS with 8+ years or MS with 6+ years relevant work experience

  • Ideal candidate will have experience on high speed, low power digital logic design with hands on experience on ASIC front end implementation tool flows and silicon bring up.

  • Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, design for test (DFT) flows for stuck and TDF modes, gate level simulation bring up and debug.

  • Position requires working closely with cross functional teams in high paced and dynamic environment to enable all phases of implementation and Si bring up.

  • Prior experience with high speed parallel physical interfaces designs and low power DDR protocols is a plus.

Education Requirements

Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering

Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.