Qualcomm RFIC Design Engineer - San Diego - QLN in San Diego, California
RFIC Design Engineer - San Diego - QLN
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
California - San Diego
Qualcomm is the world leader in wireless chipsets powering the majority of 3G & 4G devices, the largest fabless semiconductor in the world, and is widely regarded as one of the most employee friendly companies in the world. Qualcomm designs the most advanced radio technology in the commercial wireless marketplace, from LTE to Bluetooth, and QCTs RF/Analog IC Design Team is actively seeking several RFIC designers at all experience levels with demonstrated experience in the latest designs and design tools.
Design and develop the next generation of highly integrated RF integrated circuits (RFICs) using Cadence tools in deep sub-micron (65/45nm) CMOS processes. As a Design Engineer, you will play a significant role in designing RFIC solutions for rapidly expanding markets in Wireless Connectivity (Bluetooth, UltraWideBand), Consumer Electronics, 3G and 4G Cellular. Come be a part of a team that is changing the way we live and communicate.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
MSEE + up to 8 years of professional experience in the design of custom RFIC and Analog circuits in CMOS at process nodes 65nm and smaller using Cadence design tools is required.
PHD + up to 4 years of professional experience in the design of custom RFIC and Analog circuits in CMOS at process nodes 65nm and smaller using Cadence design tools is required.
Academic or professional experience in RFIC circuit design, IC design tools and simulators, and IC layout design, techniques, and verification methodologies is required.
Academic or Professional experience in RF/Analog circuit design in sub-90nm CMOS technology required.
Experience with front-end RF and Analog circuit blocks such as LNAs and Mixers, TX modulators and driver amplifiers, Frequency Synthesizers/Phase Lock Loops(PLLs), Continuous-Time Filters and ADC/DAC designs is required.
The following experience is preferred but not required:
Academic or Professional experience with CDMA2000, 1X-EVDO, WCDMA, UMTS, and GSM/GPRS/EDGE chipsets.
Academic or Professional experience with Wireless Connectivity Technologies.
MSEE + 0 - 8 years of experience
PHD + 0 - 4 years of experience
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.