Qualcomm Processor RTL Design Engineer in San Diego, California
Processor RTL Design Engineer
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
California - San Diego
Qualcomm CDMA Technologies, a.k.a. QCT - http://www.qualcomm.com/qct/, is the world leader in wireless ICs powering the majority of 3G & 4G devices, is the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortunes list of 100 Best Companies to Work For. The QCT DSP team designs high-performance, low-power digital signal processor cores which are integrated into Qualcomms products to provide unique power/performance tradeoffs.
This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor design and development is a definite advantage.
Work with architecture team to define micro-architecture for various blocks of DSP core
Develop RTL for multiple logic blocks of a DSP core and sub-system for SoC integration
Run various frontend tools to check for linting, clock domain crossing
Work with physical design team on design constrain and timing closure
Work with low power team on power optimization
Work with verification team to collaborate on test plan, coverage plan, and coverage closure
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
Must have minimum two years of practical experience with details of RTL development (VHDL and/or Verilog) including:
Functional and structural RTL design, design partitioning simulation and regression, collaboration with design verification team.
Must have experience or extensive familiarity with latest RTL languages and tools, including: simulation systems (e.g. Modelsim, VCS)synthesis tools (e.g. Design Compiler, Physical Compiler)static timing tools (e.g. Prime Time)
Experience with the following disciplines is highly desirable:
-L2 cache, memory coherency and bus protocol
-Excellent verbal and written communication skills.
-Ability to work in a team environment.
-Good self-direction and time management skills
Master's degree in Computer Engineering/Electrical Engineering required.
Doctor's degree in Computer Engineering/Electrical Engineering preferred.
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.