Qualcomm Imaging R&D ASIC Lead Design Engineer in San Diego, California

Job Description:

Job Id

E1963999

Job Title

Imaging R&D ASIC Lead Design Engineer

Post Date

05/01/2018

Company


Division

Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware

Location

California - San Diego

Job Overview

Qualcomm's Imaging R&D and Standards Group is seeking candidates for its hardware design team in San Diego, CA. The team develops new algorithms, programmable architectures and systems for image processing. We are seeking a candidate to lead our programmable logic group that will be responsible for the block design and integration while still contributing at the RTL level. Responsibilities: The selected candidate will have the following responsibilities:

  • Responsible for block level/full chip integration and design

  • Develop micro-architecture and design specifications

  • Linting, CDC, LEC and preferably Low Power check tools to implement design and check design quality

  • Develop and debug synthesis and timing constraints, review clocks, timing closure and working on design implementation flows and tools (Synthesis, STA, and DFT)

  • Using database management flows with Clearcase/Perforce/SVN

  • Work with functional verification team to review test plans and coverage

  • Implement design blocks in Verilog or SystemVerilog RTL and implement local testbenchs to test and debug designs

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications

  • Bachelor's degree in Science, Engineering, or related field.

  • 7+ years ASIC design, verification, or related work experience.

Preferred Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.

  • 12+ years ASIC design, verification, or related work experience.

  • 3+ years experience with architecture and design tools.

  • 3+ years experience with scripting tools and programming languages.

  • 3+ years experience with design verification methods.

  • 2+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above)

Education Requirements

Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering,

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.