Qualcomm SoC Power Integrity and Systems Engineer - QCT, Cork, Ireland (M) in Cork, Ireland
SoC Power Integrity and Systems Engineer - QCT, Cork, Ireland (M)
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
Ireland - Cork
Qualcomm CDMA Technologies, a.k.a. QCT - http://www.qualcomm.com/qct/, is the world leader in wireless ICs powering the majority of 3G & 4G devices, is the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortunes list of 100 Best Companies to Work For.
Qualcomm SOC Power Integrity group is looking for an exceptional engineer to work on power integrity analysis and optimization of next generation of application processors, graphic processors and modems for mobile, auto and wireless LAN platforms.
Job responsibilities include
SOC floor planning
Package /PCB optimization
Silicon package PCB co-design.
Bachelor's degree in Science, Engineering, or related field.
5+ years ASIC design, verification, or related work experience.*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfil the principal duties of the role and possesses the required competencies.
Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.
7+ years ASIC design, verification, or related work experience.
2+ years experience with architecture and design tools.
2+ years experience with scripting tools and programming languages.
2+ years experience with design verification methods.
1+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
5+ years ASIC design, verification, or related work experience.
5-7 years of experience in semiconductor industry, Packaging, PCB & Power integrity analysis and measurements
Master's or PhD in Electrical Engineering focused on electromagnetics, signal integrity or power grid optimization strategy
Solid understanding of package and PCB design techniques including optimal layer stack-up and PWR/GND plane/island assignments to minimize voltage noise.
Solid understanding of power integrity concepts, methodologies, on chip and off chip decoupling schemes
Experience in power integrity analysis on main digital domain including application processors, graphic processors and modems.
Experience in presenting design trade-off analyses and implementation recommendations with custom circuit designers
Expertise in using Agilent ADS, Hspice and Cadence/Mentor extraction tools
Understanding of measurement techniques including VNA and time domain measurements
Knowledge of SOC floor planning and required tradeoffs
Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering
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