Qualcomm Design Flow Development (PDCAD Timing) – Staff Engineer - QCT, Cork, Ireland (D) in Cork, Ireland

Job Description:

Job Id

E1963513

Job Title

Design Flow Development (PDCAD Timing) – Staff Engineer - QCT, Cork, Ireland (D)

Post Date

05/21/2018

Company


Division

Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware

Location

Ireland - Cork

Job Overview

Qualcomm's Design Flow Development team defines and enables the RTL to GDSII implementation flows for variety of advanced low power and high performance SOCs, enabling state-of-the-art mobile chipsets from Qualcomm.

The Design Flow Development team is looking for outstanding engineers with experience in timing verification and library modeling. The candidate will drive best-in-class Timing sign-off flows for >1billion device SOCs in 10nm FinFET and smaller technologies.

Responsibilities and Experience:

The engineer will be member of team developing Timing closure methodologies and flow:

  • Enhance STA technologies and design closure methodology for Mega SoCs with unique challenges driven by Low power architecture, Si Variation, Low voltage operation of mobile SoCs.

  • Drive accuracy of Liberty and interconnect modelling for on-chip device and interconnect variation

  • Spice based accuracy qualification including circuit test bench generation, Monte Carlo spice simulations, data processing using MATLAB and Perl

  • Statistical analysis techniques (POCV/SBOCV) LVF models generation and qualification

  • CAD automation for timing data mining and processing

  • Participating in project proposal development including key milestones and deliverables

  • Execute and deliver project goals in a timely manner

  • Resolve issues in all phases of development to assure smooth project execution

  • Bachelor's degree in Science, Engineering, or related field.

  • Solid ASIC design, verification, or related work experience.Solid experience within the following:

  • ASIC design, verification, or related work experience

  • architecture and design tools

  • scripting tools and programming languages

  • design verification methods

  • work experience in a role requiring interaction with senior leadership (e.g., Director level and above)

Minimum Qualifications

  • Bachelor's degree in Science, Engineering, or related field.

  • 5+ years ASIC design, verification, or related work experience.

Preferred Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.

  • 8+ years ASIC design, verification, or related work experience.

  • 2+ years experience with architecture and design tools.

  • 2+ years experience with scripting tools and programming languages.

  • 2+ years experience with design verification methods.

  • 1+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfil the principal duties of the role and possesses the required competencies.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering.

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