Qualcomm PD Engineer in Chennai, India
Job Id T1959806
Job Title PD Engineer
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location India - Chennai
Overview Qualcomm's Physical Design Engineering Team is responsible for the drive and execution of all phases of the complete physical design flow for MSM/MDM/CSMs at the core and chip-level. We are actively seeking candidates for multiple Physical Design positions in Chennai, India Responsibilities: You will be part of a team responsible for the complete Physical Design Flow for mobile /automotive chips. Tasks involved can be one or more of the following:
• Work with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation.
• Work with the DFT team on understanding DFT design in regards to physical design timing closure.
• Lead core and Top level timing closure activities.
• Develop new scripts/flows to improve the timing closure process.
• Complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR.
• Low-power implementation methods.
• Core and Top level Floorplanning, placement, CTS, P&R, PV, and Signal Integrity Analysis.
• Develop high speed customized logic cells. Skills/Experience: 2+ years of industry experience in the following technical areas:
• Physical design implementation (Floorplanning, CTS, STA) for CPUs and GPUs in advanced technologies.
• STA tool and timing closure methodologies
• Power grid, clock tree, and low-power reduction implementation methods
• Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing
• Floorplanning, Placement, CTS
• Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
• Programming and scripting skills (Tcl, perl and/or C)
• Strong verbal and written communication skills Preferred Qualifications: 3+ years of industry experience in one or more of the following technical areas:
• Power-aware yield estimation
• Vmin optimization
• Power recovery
• Technology comparison PPA analysis and sweeps
• Semicustom design of structured blocks
• Clock tree analysis and optimization
• Library analysis and evaluations
• Timing analysis methodologies
Education Requirements Bachelors/Masters in Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.