Qualcomm Power Verification Engineer/Lead in Bangalore, India

Job Description:

Job Id

E1963047

Job Title

Power Verification Engineer/Lead

Post Date

04/03/2018

Company


Division

Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Verification

Location

India - Bangalore

Job Overview

Design Verification of SOC Power Management block and power modes supported by design

  • Will work on Power Aware RTL and GLS simulations bring-up at SOC level

  • Own power coverage and assertions

  • Develop Functional test plans for the various functional areas and features

  • Develop constrained random verification tests and directed tests and ensure that functional coverage, code coverage and performance goals are met Develop formal verification strategy, create properties and constraints for IP cores. Working knowledge of Formal tools will be plus.

  • Work with Architecture and Design Engineering teams and ensure that IP cores work as per the standard Perform gate level and back annotated timing simulations.

  • Work closely with Design Engineering Team, Architects, Validation and Software teams and ensure robust verification of IP cores in a subsystem Assist in post silicon bring-up and debug

Minimum Qualifications

4 -12 years of experience in ASIC/SoC Design Verification including:

  • AMBA protocol knowledge ->AXI/AHB/APB protocols

  • Experience using latest Verification methodologies such as System Verilog, and UVM.

  • Basics of UPF and its constructs, Power Aware verification exposure

  • Exposure to Power Concepts, Retention, Isolation, Level Shifter, Power States and its functional intents

  • Power Aware GLS and its challenges

  • Working knowledge in one or more of the following: C, C++, Python, TCL or Perl.

  • Experience in scripting for automation of design methodologies & flows.

  • Positive attitude and sound aptitude, willing to perform under challenging environment and ready to show ownership.

Preferred Qualifications

4 -12 years of experience in ASIC/SoC Design Verification including:

  • AMBA protocol knowledge ->AXI/AHB/APB protocols

  • Experience using latest Verification methodologies such as System Verilog, and UVM.

  • Basics of UPF and its constructs, Power Aware verification exposure

  • Exposure to Power Concepts, Retention, Isolation, Level Shifter, Power States and its functional intents

  • Power Aware GLS and its challenges

  • Working knowledge in one or more of the following: C, C++, Python, TCL or Perl.

  • Experience in scripting for automation of design methodologies & flows.

  • Positive attitude and sound aptitude, willing to perform under challenging environment and ready to show ownership.

Education Requirements

B Tech/ M Tech

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