Qualcomm FPGA / ASIC Apps Engineer to Staff Engineer (CAE) in Bangalore, India

Job Description:

Job Id

E1963939

Job Title

FPGA / ASIC Apps Engineer to Staff Engineer (CAE)

Post Date

04/26/2018

Company


Division

Qualcomm Technologies, Inc.


Corporate Engineering at http://www.qualcomm.com/about/businesses/qces

Job Area

Engineering - Hardware

Location

India - Bangalore

Job Overview

We are building a local EDA team and have multiple openings for experienced engineers to provide internal support of the design tools used by electrical engineers. The successful candidates will become key members in QCAE (Qualcomm's Computer Aided Engineering Group), responsible for providing process automation, design services, methodology support, project consulting, and training for Qualcomm's substantial EDA tool portfolio. The engineers will work within a global team of experienced EDA support engineers. They will drive automation and troubleshooting related to the design flows QCAE supports. Working effectively across organizational boundaries is essential, as is the effective documentation and presentation of results. Candidates are needed to support the following design flows: FPGA - Commercial tools and custom tools to support FPGA design entry, simulation, synthesis, implementation, configuration, and debugging. ASIC front end - Commercial tools and custom tools to support ASIC design entry, simulation, synthesis, linting, formal verification and timing analysis.

Minimum Qualifications

*3+ years actively involved in supporting FPGA tools and ASIC front end tools

*Coding experience with C, and/or Python, and/or Java, shell and/or TCL programming experience

*Familiar with Windows and Linux operating systems and environment.

*Good verbal and written communication skills

Preferred Qualifications

*Hands-on experience with Xilinx and/or Altera FPGA devices.

  • Demonstrated experience on tools such as Xilinx Vivado, Altera Quartus

  • Prior experience on support for any simulation tools such as Questsim/Modelsim, VCS, Incisive

  • Prior experience on support for any synthesis tools such as Synopsys Synplify, Design Compiler

*Prior experience on supporting Timing Designer

*Previous experience to create custom scripts or parsers that augment FPGA and ASIC tools

  • Strong problem solving/ debugging skills.

  • Effectively communicates with project peers and engineering personnel via e-mail, web meetings, and instant messaging including status reports and illustrative presentation slides.

  • Leadership skills to help direct, prioritize, and clearly set project tasks per schedule. Communicate milestones and directions to outside team members.

Education Requirements

Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.