Qualcomm Design Verification Engineer, Staff in Bangalore, India

Job Description:

Job Id


Job Title

Design Verification Engineer, Staff



Qualcomm Technologies, Inc.

Corporate Research & Development at http://www.qualcomm.com/about/research

Job Area

Engineering - Hardware


India - Bangalore


Job Function

Join Qualcomm Research India and become part of an innovative global company. QUALCOMM is consistently ranked as one of Fortune's 100 Best Companies to work for. QUALCOMM develops, manufactures, markets, licenses, and operates advanced communications systems and products based on its digital wireless technologies. By partnering with other companies and acting as an enabler to their business activities, QUALCOMM acts as a catalyst to the entire wireless industry.

QUALCOMM Research has a mission to evaluate and help commercialize advance technologies found in our chipsets including: wireless communication, computer architecture and micro-architecture, modem architecture and micro-architecture, low power VLSI design, SOC modeling, RF, signal processing (algorithm design/modeling), cryptographic hardware, networking, computer vision, augmented reality, and sensors. The work environment is fast paced and dynamic so the candidate should be flexible in their work assignments and task priorities. The ability to learn new technical skills and a willingness to adapt to new projects is crucial.

Responsibilities :

The candidate should be able to lead a team of engineers to test and verify hardware and SOC solutions technologies for next generation mobile chip sets.

Responsibilities include: Design and develop verification environment components, and write, execute and debug tests from testplans or functional specifications. Work directly with various project teams to assist with the deployment of design-for-verification methodologies.

Verification components to be developed may include bus functional models/agents/bus interface models, data/transaction and sequencers, bus monitors, checkers/scoreboard, coverage models, and assertion libraries


9 to 18 years experience in Design Verification with multiple design cycles in ASIC flow is required.

Must possess knowledge of design-for-verification methodologies. IC verification experience should include use of modern verification techniques, tools, and languages. Must be skilled in System Verilog, SystemC or, C++/OOP, and have a strong background in data structures and algorithms. Hands-on chip verification experience is required. Experience with verification methodologies like OVM/UVM is desired. Chip design experience using industry-standard hardware description languages (Verilog/VHDL/System Verilog) is desired.

Experience in scripting languages, preferably Perl, Python, Tcl, etc is preferred.

Excellent oral and written communication skills.

Education Requirements

Required: Bachelor's, Electrical Engineering

Preferred: Master’s, Electrical Engineering

Education Requirements

Required: Bachelor's, Electrical Engineering

Preferred: Masters, Electrical Engineering

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.