Qualcomm DDR-PHY Front End Design Lead/Architect in Bangalore, India
Job Id E1961816
Job Title DDR-PHY Front End Design Lead/Architect
Post Date 02/01/2018
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location India - Bangalore
Job Overview - Architecture, design and development of high performance, low power PCDDR/LPDDR PHYs in cutting edge technologies
Architecture study and design trade-off analysis to align with product requirements & roadmap
RTL Design, Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks.
Establish solid design process, design reviews & verification flow to drive productivity & quality
Minimum Qualifications - Must have experience with RTL logic design. Must have 7-15 years of practical experience with STA (preferred in PrimeTime)
Good understanding of PDDR2/3/4 & LPDDR2/3/4 standards and constraints
Exposure to high speed custom building blocks for the DDR PHY
VLSI circuit design understanding
Familiarity with package/board constraints is a plus
Excellent communication skills and ability to work across multiple teams in multiple locations
Preferred Qualifications NA
Education Requirements Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.