Qualcomm ASIC Timing Methodology/Sign-off Lead/Specialist in Bangalore, India
ASIC Timing Methodology/Sign-off Lead/Specialist
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
India - Bangalore
Experienced STA/Timing Engineer with 4-8 years of hands-on experience on timing methodology/sign off/convergence for complex SOCs
Work on timing sign off, convergence, methodology development and related automation.
Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.
4+ years Hardware Engineering experience or related work experience.
4 -8 yrs of hands-on experience and ability to hit the ground running.
Good communication and technical writing skills, along with proven ability to collaborate with timing methodology and Physical design teams across multiple sites
Have experience in driving timing convergence at Chip-level and Hard-Macro level
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
Extensive hands-on experience with STA tools - Prime-time, Tempus
In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling
In-depth knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
Working knowledge of ASIC back-end physical design flows and methods and tools (ICC2, Innovus)
Proficient is scripting languages TCL, Perl, Awk, Python
Basic knowledge of device physics
Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.