Qualcomm ASIC Design Lead (Test Chip/IP Design & Implementation) in Bangalore, India
ASIC Design Lead (Test Chip/IP Design & Implementation)
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
India - Bangalore
Design Engineer/lead to take care of Front end design activities.
Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
Work closely with Technology/circuit design team to close IP block specification/requirement.
Work closely with DFT/Design verification/physical design team to complete the Testchip design implementation.
Work closely with system/software/test team to enable the low power feature in wireless SoC product.
Understand and perform block & chip-level power analysis
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.
5+ years Hardware Engineering experience or related work experience
Good Knowledge of Verilog, VHDL syntax -- RTL and Netlist parsing
Working knowledge of multi power domain design
Expertize in the synthesis constraints
Experience in the synthesis flows and power aware synthesis
Good knowledge of standard cell/memories/macros .lib models and usage for synthesis
Synopsys DC/PT tool setup and hands on synthesis experience
Clock definitions, multi clock domain definitions
Exceptions handling - MCP, False paths
IO timing definition, Skew budgeting
Syntax and working knowledge of power intent files UPF/CPF files
Formal verification of RTL vs Netlist, Netlist vs Netlist
Experience in front end flows like spyglass LINT, CDC checks
Static timing Analysis is a plus point
Required: Bachelor's, Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.