Qualcomm Analog Layout Lead in Bangalore, India
Analog Layout Lead
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering - Hardware
India - Bangalore
Qualcomm Technologies, http://www.qualcomm.com/qct/, is the world leader in wireless ICs powering the majority of 3G & 4G devices, is the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortunes list of 100 Best Companies to Work For. QCT is actively seeking experienced mixed-signal design candidates for the low-power implementation team. This team is responsible for developing new low-power techniques and technologies for wireless communication chipsets. The team also contributes to the development of front-end design flows for QCT.
Candidate should be able to successfully execute all full custom layout activities but not limited to layout floor planning, signal planning, power planning and physical verification leading to a successful module signoff.
Candidate should have strong analog layout fundamentals and focused exposure to handling multi voltage domain circuit layouts, latchup and ESD aware layout development strategy.
6 to 9 years of relevant experience in RF/Analog/PMIC Layout.
Candidate must have strong hands on experience on using EDA tools viz. Cadence Virtuoso XL, Cadence Schematic Editor, Cadence Virtuoso Assembly Router, Mentor Graphics Calibre Verification Suite, StarRC. Experience on Silicon Frontline Tool is a plus.
Candidate must have strong written and oral communication skill. Ability to work with people from different time zone and being a multitasking strong team player is a desired plus.
Candidate should be able to supervise junior layout resources, schedule and plan layout activities leading to a successful module release for Chip Integration.
Candidate should be able to handle work pressure, be a great team player and an asset to the organization in the long term.
Understanding of electrical engineering concepts, analog and mixed signal circuits.
Understanding of deep submicron CMOS processes.
Familiarity with 28nm and beyond layout techniques.
Able to clearly explain ideas and communicate.
Work in a dynamic, team oriented environment.
Highly organized and able to multi-task.
Required: Bachelor's, Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.