Qualcomm WiFi Baseband Designer Senior or Staff in Shanghai, China
Job Id E1956948
Job Title WiFi Baseband Designer Senior or Staff
Post Date 07/12/2017
Company-Division Qualcomm Atheros Inc
Qualcomm Atheros at http://www.qualcomm.com/about/businesses/qca
Job Area Engineering - Hardware
Location China - Shanghai
Job Overview The candidate will be responsible for the ASIC design and co-verification of various 802.11 wireless baseband IPs within current and next generation wireless products. The candidate will work within the local DSP/digital development team and closely with system/simulation/verification/RF engineering teams in US to develop and implement DSP/digital blocks to build WiFi IPs.
Job responsibilities includes: spec development and design of DSP/digital blocks, developing co-verification platforms, performing simulations, and solving integration and testing problems during the development, characterization, and production stages of the product. Successful candidate must have the ability to communicate with engineers of various backgrounds: systems, software, digital hardware, RFIC design, and verification.
Minimum Qualifications Extensive hands-on experience in the development of Wireless baseband IC design. WIFI baseband design experience is preferred. The candidate must have at least 6-years development experience on wireless baseband design. WiFi 802.11 n/ac design experience is a plus.
Deep knowledge and good understanding of: digital communication theory, information theory; specifically on: equalization, Fourier transform, spatial-temporal coding, linear and maximum-likelihood estimation, Viterbi decoding, frequency/ timing estimation and calibration, automatic gain control, transmitter beam forming, diversity combining, and their high-speed DSP/digital implementation.
Extensive experience with RTL programming languages.
Experience with verification methodologies and tools and advanced complex RTL/C test-bench developments. The familiarity with UVM environment is a plus.
Experience with developing algorithms in C, C++, and Mat lab.
Experience with scripting language such as Perl, Python.
Must have experience with lab testing and characterization of digital sub-systems.
Candidate must have strong English communication skills with willingness to interact with various groups within the company.
Experience with physical design flows, tools, methodologies, and development of timing constraints is a plus.
Familiarity with flows and tools for co-simulation of RTL and C models is a plus.
Familiarity with testing and integration of RF and baseband systems in the lab is a plus.
Experience with implementation of calibration modules for RF/Analog blocks is a plus..
Typically requires a Master degree and 6 years of experience or a PhD and 3 years, in VLSI/ASIC architecture design or ASIC implementation of digital signal processing function.
Preferred Qualifications NA
Education Requirements NA
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.