Qualcomm PHY Design Verification Engineer in San Jose, California
Job Id E1956947
Job Title PHY Design Verification Engineer
Post Date 07/13/2017
Company-Division Qualcomm Atheros Inc
Qualcomm Atheros at http://www.qualcomm.com/about/businesses/qca
Job Area Engineering - Verification
Location California - San Jose
Job Overview Qualcomm' WiFi digital ASIC team delivers cutting edge hardware and software products across every established wireless connectivity technology (WiFi, BT, FM, NFC etc). We are currently seeking talented candidates for digital architecture, design, implementation, and verification of next-generation Wireless LAN devices. This is for a Design Verification position for the PHY team.
As a key member of Verification team you will be involved in all or some of a) PHY layer verification b) developing the methodology & verification infrastructure c) developing components. The components must be developed using advanced verification techniques that enable reuse of test benches and environments across simulation, simulation acceleration, emulation and post silicon validation.
Minimum Qualifications Required:
At least 5 years of experience in ASIC verification including:
Verification methodology using System Verilog, SVA, OVM/ UVM, Vera, or VMM
Experience in writing feature based test plans and implementing such test plans using one of the methodologies listed above
Experience running regressions, debugging test failures and achieving test plan targets
Preferred Qualifications - Experience with DSP design/verification a plus
- Experience with WiFi or LTE desirable
Education Requirements Required: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering or equivalent experience
Preferred: Doctorate, Computer Engineering and/or Computer Science and/or Electrical Engineering or equivalent experience
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.