Qualcomm Timing Design for DDR PHY Engineer, Senior in San Diego, California
Job Id E1946285
Job Title Timing Design for DDR PHY Engineer, Senior
Post Date 06/05/2017
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location California - San Diego
Job Overview Job overview:
The QCT team is focused on development of - DRAM memory interface for all Qualcomm projects. This position requires involvement in all aspects of front-end and physical , guiding the team on timing considerations from architecture through tapeout. Responsibilities include:
a.Identification and analysis of timing bottlenecks and mitigation solutions.
b.Guidance to front-end and physical teams on all aspects of timing considerations.
c.Development and support of PrimeTime STA timing constraints.
d.Execution of Star-RCXT/PrimeTime flow for analysis and sign-off.
e.Development of system timing budget and application to internal constraints.
f.Development of scripted automation for efficient data and waiver processing.
Minimum Qualifications 3+ years of practical experience with static timing analysis(STA) and PrimeTime constraints development.
logic and physical .
VLSI circuits understanding, including Spice analysis.
operation and timing considerations.
Preferred Qualifications Unix/Perl/TCL scripting (must be comfortable with writing scripts)
Excellent communication skills and ability to work across multiple teams across global locations.
Education Requirements Bachelor's degree in Electrical Engineering required, Master's preferred
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.