Qualcomm Strategic technology TCAD engineer in San Diego, California
Job Id E1956859
Job Title Strategic technology TCAD engineer
Post Date 07/07/2017
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Manufacturing/Quality/Other
Location California - San Diego
Job Overview This position is for a technical individual contributor in QTI process technology team for advanced CMOS strategic technology development. Candidates will be responsible for TCAD based technology assessment of advanced CMOS nodes including competitive technology selection with best device and circuit FOM (performance/watt/cost), benchmarking of process modules and integration flows for manufacturability/cost evaluation, and identification/development of key enabling technologies with foundry partners and external collaborators at universities and/or consortia.
Primary responsibility is to lead TCAD based evaluation and screening og multiple technology options for n+1 and beyond generation
Technology definition, such as key process module, process integration flow, DC/AC device target and design rules, for QTIs next generation product.
Figure of Merit (FOM) development and evaluation at process, device and circuit level.
Work together with foundry partners and external collaborators (at universities/consortia) for key technology definition and evaluation.
Technical reporting, documentation (patent, publication) and process transfer to internal technology enablement team.
Minimum Qualifications Minimum of 5 years of TCAD (process/device/structural) experience developing advanced CMOS process, device, or circuit. An advanced industry related engineering or science degree is preferred and may reduce the level of experience required preferred.
Preferred Qualifications - Demonstrated understanding of the CMOS device physics and basic circuit operation including SRAM and other logic gates.
Extensive knowledge of FEOL and BEOL unit processes including Dielectric deposition, Lithography, Etch, PVD/CVD deposition, implant, CMP, etc.
Working understanding of the ground rules, design manual, and reliability.
Experience in optimizing CMOS process integration flow of advanced nodes for manufacturability and yield.
Experience in on SPICE simulation is a plus.
Excellent communication skills.
Demonstrated ability to meet deadlines and commitments.
Education Requirements M.S. degree or Ph.D. in Electrical Engineering, or related field.
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.