Qualcomm R&D Design Technology Integration Engineer in San Diego, California

Job Description:

Job Id E1957462

Job Title R&D Design Technology Integration Engineer

Post Date 07/28/2017

Company-Division Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location California - San Diego

Job Overview Join this team focused on RF Front End Modules for the Cellular and Wireless Data markets. You will be part of the Business Unit Engineering organization, and work directly with and support multiple product development teams.

Position requires a senior technical specialist who can provide leadership in the development of new and sustainable technology platforms for the company using a solid background in materials, device physics, front end and back end processes, and supplier interactions.


Exhibit skill and confidence in working cross-functionally across a matrix organization in a very dynamic and fast-paced environment.

Support development of advanced technologies for RF-SiP applications.

Lead all aspects technology integration in to PAMIDs, perform technical risk assessment, launch mitigation plans and ensure yield and reliability metrics are met and are in line with PAMID release schedules.

Understand substrate and assembly Packaging process details, SPC, Control plans, OCAPs, FMEAs, PCN, CARs and Quality metrics. Conduct audits, benchmarking and drive best practice methodologies to proactively prevent quality excursions as the technology ramps.

Team cross-functionally with, Design, Device process development, Packaging, FEA and global NPI teams to support technology readiness for new products

Ideate, Sketch and Participate in value engineering and cost reduction plans along with Qualcomm Packaging and Sourcing teams.

Create, conduct, and analyze Design of Experiments (DOE) for development activities, especially those that relate to filter performance as it impacts module behavior.

Ensure product readiness for ramp. Protect product integrity post ramp.

Minimum Qualifications 15+ years of experience desired (20 preferred) in electronics packaging in related environments, especially RF module industry. Direct experience with RF-mems, SAW / BAW configurations.

At least 10 years direct experience in process engineering, product integration or quality management at tier 1 foundries, assembly sub-contractors or substrate suppliers.

Solid technical understanding of full range of Semiconductor packaging materials, material interactions, processes, dominant failure mechanisms and analytical techniques.

Good knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI).

Preferred Qualifications Familiarity with PCB design and layout tools preferred.

Understanding of package/product qualification and reliability methods and failure analysis is required.

Understanding of statistics, control methodology, FMEA, analytical trouble shooting in a factory environment is required.

Excellent communication skills.

Willingness to travel internationally, typically once per quarter.

Education Requirements Required: Master's, Electrical Engineering and/or Materials Science and/or Mechanical Engineering


EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.