Qualcomm Packaging/System Integration Engineer (San Diego or San Jose) in San Diego, California
Job Id E1954835
Job Title Packaging/System Integration Engineer (San Diego or San Jose)
Post Date 04/14/2017
Company-Division Qualcomm Technologies, Inc.
Corporate Research & Development at http://www.qualcomm.com/about/research
Job Area Engineering - Hardware
Location California - San Diego
California - Santa Clara
Job Overview Corporate Research & Development team at Qualcomm has an opening for an Electrical Engineer with experience in system in package design, integration and fabrication. The successful candidate for this position will be responsible for:
Electrical design aspects of multi-chip system in package (SIP) for wearables, biomedical implants and mobile applications
Create, maintain system level product requirements, complete design feasibility studies and package simulations
Create package design solutions and undertake engineering analysis and experiments to demonstrate package performance and reliability
Select materials, process, tools and vendors. Manage functional and electrical prototype builds. Conduct on-site vendor visits to support prototype builds
Identify failure modes, design experiments to quantify and/or resolve failure modes, demonstrate functional prototypes.
Conduct analysis, develop electrical models to predict package performance and refine package design to meet product requirements.
Evaluate die & packages, validate models and demonstrate performance against product requirements
Work closely with die, package and system teams to deliver optimized SIP package while meeting aggressive form factor & performance requirements.
Participate in the product development cycle by documenting & communicating system-level performance issues.
2 years experience in electrical design of packages (PhD in Engineering would be acceptable in lieu of the experience)
Broad exposure to electrical design and transforming product design concepts into products
Knowledge of advanced system in package but not limited to interposers, stacked die packages, 2.5D/3D package, through silicon/glass via packages
Demonstrated ability to work at leading edge in package development with track record of innovation
Extensive knowledge of electrical design with in-depth experience in electromagnetic (EM) simulation.
Experience in software design tools such as Cadence SIP, Q3D, LT-Spice, HFSS, Altium, Allegro.
Extensive experience with HFSS and other EM simulation tools desired. Ability to develop EM simulations and validate with model-hardware correlations.
Knowledge of signal integrity and power delivery for advanced multi-chip system in package
Experience with electronics component selection and defining components for use in electronic system in wearables, implants and mobile electronics
Familiarity with PCB layout methodologies for electronic product design, particularly for multi-chip system-in-packages. Demonstrated ability in package design software such as Cadence preferred
Demonstrated ability to perform wafer level and board level measurements
Demonstrated ability to design experiments to identify failure modes, iterate and refine designs to improve package performance
Ability to evaluate and down select tools & processes while making trade-off decisions between processes to optimize package reliability, performance and cost.
Ability to function with minimal supervision and take technical lead while working collaboratively in a global design and fabrication system
Ability to create and meet product development schedules
Experience or strong familiarity with SMT/SMD & other electronic manufacturing methods.
Effective communication skills with cross functional teams on both technical and non-technical product design topics.
Ability to support multiple projects simultaneously
Medical device packaging experience preferred
Education Requirements Required: Bachelor's, Electrical Engineering and/or Materials Science and/or Mechanical Engineering
Required: Master's, Electrical Engineering and/or Materials Science and/or Mechanical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.