Qualcomm IC Package Design DFM Integration Engineer (Staff) in San Diego, California
Job Id E1957466
Job Title IC Package Design DFM Integration Engineer (Staff)
Post Date 10/06/2017
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location California - San Diego
Job Overview The IC Package Architecture Design team has an opening for Package Design DFM Engineer. This team is responsible for Package technology planning, architecting, design methodology, design implementation, verification, and DRC development for Qualcomm package products
Job responsibilities for this position include concept analysis for new products, design verification & validation methodology, technology roadmap planning, package assembly & substrate rule development, and technology test vehicle design.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
7+ years of IC package selection, package design and layout experience in 2-6 layer laminate substrate technologies (BGA and LGA)
Experience with assembly and substrate manufacturing processes, package technology trade-off, design rules in wire bond, flip chip, or SiP/Module.
Experience in Package DRM & DRC development and technology test vehicle design, package design flow, verification & validation methodology.
Package level netlist capture and mechanical/electrical constraint management
Package level thermal performance and enhancement techniques
System level co-design methodology of IC, Package and PCB/Board
Package pinout optimization incorporating system level trade-offs of pad/bump assignment, package routing and PCB target component pinouts
Working with marketing/IC/product teams on competitive analysis and road mapping package technology for future products
Experience in concept analysis for new product package selection based on requirements for mechanical, thermal and electrical performance with the goal to achieve system level cost vs. performance balance.
Understanding of package cost structure.
Design layout understanding of PCB breakout
Understanding of package reliability requirements.
Tolerance Stack up analysis
Geometric Dimensioning and Tolerancing (GD&T) basic knowledge
IC top level floor planning including RDL and bump pattern/assignment
PCB level analysis affecting package array/pinout, PCB fanout, PCB stack-up, and analysis of de-cap placement (internal or external)
System level knowledge of mobile architecture and understanding of trade-offs made for partitioning of the key devices (Digital Baseband, Digital Apps Processor, RF, PA, PMIC, Audio, etc...)
Package Design expertise in SIP/Module in 2-4+ layer laminate substrate technologies (BGA & LGA)
Package design flow methodology implementing system constrain, isolation, current distribution, and RLC spec.
Hands-on experience in package signal integrity SI/PI model creation, simulation, and design constrain implementation.Software:
Cadence SiP/APD (including Constraint Manager)
Mentor Valor, Cadence Ravel, or CAM350 equivalent DRC tool.
Operating Systems: UNIX/Linux
Education Requirements Required: Bachelor's, Electrical Engineering and/or Mechanical Engineering
Preferred: Master's, Electrical Engineering and/or Mechanical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.