Qualcomm Hardware Design Verification - Graphics ( Santa Clara & San Diego, CA) in San Diego, California
Job Id T1954592
Job Title Hardware Design Verification - Graphics ( Santa Clara & San Diego, CA)
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location California - San Diego
California - Bay Area
Overview Qualcomm CDMA Technologies (QCT), is the world leader in wireless ICs powering the majority of 3G & 4G devices and is the largest fabless semiconductor in the world. QCT's Digital ASIC design team delivers cutting edge hardware and software products that power the user experience and graphics content of the most advanced mobile devices on the market.
Our Design Verification team is currently seeking applicants for graphics functional design verification positions that involve the development of corresponding test plans, designing and developing our verification environments, and applying these to verify complex GPGPU designs until coverage and performance goals are achieved.
As verification is a rapidly changing field and consumes majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification(static property checking), HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis.
QCT is the largest fabless design house in the world and provides hardware, software and services to nearly every mobile device maker and operator in the wireless marketplace. Our chipsets power a variety of products; tablets, smartphones, e-readers and other devices, and our digital design teams are at the core of all of them. The environment is fast-paced and requires cross-functional interaction on a daily basis so good communication, planning and execution skills are a must.
4+ years experience required in the following areas:
Verification skills: test planning, test bench architecture, assertions, problem solving and debug
Constrained Random Verification experience with SystemVerilog using OVM or UVM
Coverage driven verification(code/functional/assertion coverage)
Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting Additional skills in the following areas are a plus:
Candidates with 2D/3D graphics and compute standards, such as DirectX, OpenGL and OpenCL are preferred
RTL design experience and/or very strong OO programming experience is also a plus
Experience with simulation acceleration tool is a plus
Experience in formal verification is also a plus
Good written and oral communications skills
Education Requirements Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.