Qualcomm Design-For-Test (DFT) Careers @ Qualcomm, Noida in Noida, India

Job Description:

Job Id T1943540

Job Title Design-For-Test (DFT) Careers @ Qualcomm, Noida

Company-Division Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location India - Noida

Overview DFT team Qualcomm, India currently have multiple Design-For-Test (DFT) Engineer positions available. This team is responsible for the architecture and implementation of advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for high performance, highly integrated SoCs. Candidates selected will be directly involved with implementation of various DFT architectures to achieve high quality manufacturing tests that reduce test cost, and increase production quality. In addition, candidates selected will also be involved in all aspects of DFT including architecture, methodology development, design, vector development, manufacturing testing, and debug.


3-15 years of industry experience in the following areas are required for Senior level roles, and 15+ years of industry experience required in the areas described below for Lead level roles.

  • DFT/DFD/DFM techniques for complex SoCs

  • Fault modeling Stuck-at, Transition, Path Delay, IDDQ, and other models

  • JTAG, MBIST, IO Bist, Scan Compression, ATPG, and at-speed testing

  • Industry standard ATPG tools like Mentor TestKompress, Synopsys TetraMax, or Cadence Encounter Test

  • Industry standard MBIST tools such as Synopsys STAR or Logicvision memBIST

  • Scan insertion using DFT Advisor or equivalent

  • Logic design, Verilog RTL and verification

  • Scripting in Perl and Tcl

  • Industry standard simulation tools such as VCS, Questa or NCVerilog

  • Silicon bring-up, debug, and validation of DFT features on ATE

Desired Experience:

  • Design, insertion and verification of the DFT structures, ATPG Pattern generation, logic simulation, debug on ATE

  • Complex Server SOC DFT implementation.


  • Implementation of advanced DFT/DFD (design for test/design for debug) techniques for high performance, highly integrated SoCs.

  • Work with design teams to improve low coverage on designs to desired target.

  • Architect DFT features, including high-speed IO DFT, MBIST and functional based DFT.

  • Work with Test Engineers to debug/diagnose manufacturing defects.

Education Requirements Required: Bachelors, Computer Engineering, Computer Science, and/or Electrical Engineering.

Preferred: Masters or PhD, Computer Engineering, Computer Science, and/or Electrical Engineering.


EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.