Qualcomm Product Test Engineer, Senior in Hsinchu, Taiwan

Job Description:

Job Id E1951249

Job Title Product Test Engineer, Senior

Post Date 08/03/2017

Company-Division Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Manufacturing/Quality/Other

Location Taiwan - Hsinchu

Job Overview Job Function

Senior Product Test Engineer. Manage improvements in quality, capacity, supply assurance, cost and yield at manufacturing sub-contractors, ramping and enabling new technologies as appropriate.

1.Unit Cost Reduction:

Drive final test yield management of Connectivity products, mainly in the Bluetooth, WiFi and GPS applications.

Driving yield improvement through emphasis on Final Test KPIs and close cooperation with Foundry, PME, Test, SQE and YMT engineering teams to drive improvements in Fab process, Assembly process and Test methodology

  1. Output Plan Support:

Support Planning executing the manufacturing output plan at our SATs, providing feedback on issues affecting supply.

Work with off-shore planning team to highlight OTD problems acting as ears/eyes on the ground.

To support own products and in driving improvement activity in the ASE sites through 8D and SCR activities driven by our Quality groups.

Minimum Qualifications Minimum Qualifications:

3+ years experience in yield management, continuous improvement and cost reduction in a high volume fabless semiconductor environment

Advanced understanding of statistical process control techniques

Good understanding of semiconductor industry standards

Advanced understanding of assembly methodologies

Good understanding of Mixed-signal test and test techniques

Good grasp of modern failure and materials analysis techniques

Must be fluent in English and Mandarin, both spoken and written.

Preferred Qualifications:

Good experience with yield management software (dataPower/VSF preferred)

Basic knowledge of customer spec reviews and/or Approved Part Qualification Process (APQP) completion

Previous experience of high volume assembly/packaging engineering in the Fabless sub-contract sector

A high-level understanding of assembly methodologies for a variety of packages including Ball Grid Arrays (BGAs), Quad Flat No lead (QFN) and Wafer Level Chip Scale Packages (WLCSPs)

Preferred Qualifications NA

Education Requirements Master's degree in Electrical Engineering or equivalent.

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.