Qualcomm - Design Verification Engineers - QCT, Cork, Ireland in Cork, Ireland

Job Description:

Job Id E1947023

Job Title - Design Verification Engineers - QCT, Cork, Ireland

Post Date 10/05/2017

Company-Division Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location Ireland - Cork

Job Overview A world leader in smart mobile technologies, QCT offers complete solutions that enable continuous innovation for today's smart connected devices. Our vast expertise in wireless technology, combined with our unique systems approach to developing solutions, puts QCT at the forefront of the rapidly expanding mobile industry. QCT offers solutions for CDMA, UMTS, GSM and LTE technologies, providing support for both 3G and 4G networks and devices. Qualcomm also offers a broad portfolio of additional wired and wireless technologies for the mobile, networking, computing and consumer electronics product segments. Our combined portfolio now features an expanded array of high-performance, end-to-end solutions ranging from Wi-Fi, GPS, Bluetooth, FM and Ethernet to HomePlug Powerline and passive optical network (PON) technologies. All of our solutions and products are elegantly engineered for optimal performance and power consumption. And our system-on-chip solutions like Snapdragon bring together CPU, GPU, connectivity, multimedia and GPS technologies in a way that is redefining mobile possibilities for people everywhere. Because of its unsurpassed performance and capabilities, Snapdragon is enhancing the mobile experience and fuelling an ever-expanding array of new connected device categories, ranging from smartphones to tablets to e-readers and beyond.

Minimum Qualifications see below

Preferred Qualifications

  • Experience in design, testing and verification in hardware and software on SoCs and SoC subsystems.

  • Methodologies for verifying complex units on SoC using industry standard tools and technologies

  • Proficient in developing unit and SoC level test benches using OVM/UVM

  • Constrained random functional verification environment in System Verilog

  • Experience in Gate Level Simulation (GLS) verification flow for SoC verification.

  • Experience of pre and post-silicon verification testflow and automated test benches

  • Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog

  • Verilog, C/C++, System C, Java, TCL/Perl/shell-scripting required

  • Building and leading verification teams is a plus

  • RTL design and front end design flow experience

  • Excellent communication skills

Education Requirements Required: Bachelor's in Electrical Engineering and/or Computer Engineering

Preferred: Master's in Electrical Engineering and/or Computer Engineering

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.