Qualcomm SOC Physical Design Signoff team @ Qualcomm Chennai in Chennai, India

Job Description:

Job Id T1956420

Job Title SOC Physical Design Signoff team @ Qualcomm Chennai

Company-Division Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location India - Chennai

Overview Overview:

Qualcomm's Physical Design Signoff Engineering Team is responsible for SOC level signoff of phases of the complete physical design flow for MSM/MDM/CSMs at the core and chip-level. We are actively seeking candidates for multiple Physical Design Signoff positions in Chennai, India

Responsibilities:

You will be part of a team responsible for the complete SOC Physical Design Signoff Flow for MSM/MDM/CSM chips. Tasks involved can be one or more of the following:

• Own complete Timing convergence, Closure and Signoff for the full chip.

• Work with the RTL/DFT team on understanding design for early physical feedback to PNR team.

• SOC level Physical Verification Signoff and Closure for 28nm, 14nm, 10nm and 7nm designs.

• SOC level Powergrid analysis and signoff including RTL and inrush analysis.

• SOC Firnak Verification and Conformal Low Power (CLP)

• Scripting and methodology development for early convergence and signoff of SOC level designs.

Skills/Experience:

3 to15 years of industry experience in the following technical areas:

• Physical design implementation (Floorplanning, CTS, STA) for CPUs and GPUs in advanced technologies.

• STA tool and timing closure methodologies

• Power grid, clock tree, and low-power reduction implementation methods

• Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing

• Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification

• Programming and scripting skills (Tcl, perl and/or C)

• Strong verbal and written communication skills

Preferred Qualifications: .....

3 to15 years of industry experience in one or more of the following technical areas:

• Timing closure and ECO generation for timing using Primtime or some other industry standard tool.

• Timing Constraint analysis and budgeting for blocks.

• PDN analysis using Redhawk,

• Clock tree analysis and optimization

• Knowledge of Calibre and DRC fixes in 28nm and below.

• Timing analysis methodologies

Education Requirements Required: Bachelor's, Electrical Engineering

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.