Qualcomm Lead Engineer -Soc Synthesis in Bangalore, India

Job Description:

Job Id E1956183

Job Title Lead Engineer -Soc Synthesis

Post Date 06/15/2017

Company-Division Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location India - Bangalore

Job Overview We are looking for candidates with 5-10 yrs Experience in SOC logic synthesis and timing constraints.

You will be responsible for full chip level physical aware and power aware synthesis and timing constraints.

Requirements:

Candidate should have working knowledge of industry leading synthesis tool

Good understanding of timing constraints development and debugging

Knowledge of physical aware and power aware synthesis is desirable

Responsibilities:

Candidate will be working on Physical aware synthesis, multi-voltage, and low power synthesis flows

Candidate will be extensively involved in timing constraints development and validation using Primetime and other industry leading tools

Bottom-up and top-down constraints partitioning

Minimum Qualifications We are looking for candidates with 5-10 yrs Experience in SOC logic synthesis and timing constraints.

You will be responsible for full chip level physical aware and power aware synthesis and timing constraints.

Requirements:

Candidate should have working knowledge of industry leading synthesis tool

Good understanding of timing constraints development and debugging

Knowledge of physical aware and power aware synthesis is desirable

Responsibilities:

Candidate will be working on Physical aware synthesis, multi-voltage, and low power synthesis flows

Candidate will be extensively involved in timing constraints development and validation using Primetime and other industry leading tools

Bottom-up and top-down constraints partitioning

Preferred Qualifications We are looking for candidates with 5-10 yrs Experience in SOC logic synthesis and timing constraints.

You will be responsible for full chip level physical aware and power aware synthesis and timing constraints.

Requirements:

Candidate should have working knowledge of industry leading synthesis tool

Good understanding of timing constraints development and debugging

Knowledge of physical aware and power aware synthesis is desirable

Responsibilities:

Candidate will be working on Physical aware synthesis, multi-voltage, and low power synthesis flows

Candidate will be extensively involved in timing constraints development and validation using Primetime and other industry leading tools

Bottom-up and top-down constraints partitioning

Education Requirements Bachelors and preferred Masters .

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