Qualcomm Lead Engineer -Formal Verification in Bangalore, India

Job Description:

Job Id E1956182

Job Title Lead Engineer -Formal Verification

Post Date 06/15/2017

Company-Division Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location India - Bangalore

Job Overview You will be responsible for full chip level Formal Verification (LEC), Conformal ECO and block level synthesis.

Requirements :

-Candidate should be expert in debugging FV failures

-Should be able to handle conformal ECO generation independently.

-Good know how of power aware FV is desirable.

-Perl/tcl scripting will a plus

-Knowledge of power aware and physical aware synthesis is desirable

Responsibilities :

-Formal verification for RTL to gates and gates to gates

-UPF 2.0 based power aware equivalence checking using Conformal.

-Debugging PA-FV failures

-Conformal ECO for doing complex functional ECOs.

-Low power synthesis on smaller blocks and subsystems using DC/Genus

-Physical Aware synthesis of small blocks

Minimum Qualifications You will be responsible for full chip level Formal Verification (LEC), Conformal ECO and block level synthesis.

Requirements :

-Candidate should be expert in debugging FV failures

-Should be able to handle conformal ECO generation independently.

-Good know how of power aware FV is desirable.

-Perl/tcl scripting will a plus

-Knowledge of power aware and physical aware synthesis is desirable

Responsibilities :

-Formal verification for RTL to gates and gates to gates

-UPF 2.0 based power aware equivalence checking using Conformal.

-Debugging PA-FV failures

-Conformal ECO for doing complex functional ECOs.

-Low power synthesis on smaller blocks and subsystems using DC/Genus

-Physical Aware synthesis of small blocks

Preferred Qualifications You will be responsible for full chip level Formal Verification (LEC), Conformal ECO and block level synthesis.

Requirements :

-Candidate should be expert in debugging FV failures

-Should be able to handle conformal ECO generation independently.

-Good know how of power aware FV is desirable.

-Perl/tcl scripting will a plus

-Knowledge of power aware and physical aware synthesis is desirable

Responsibilities :

-Formal verification for RTL to gates and gates to gates

-UPF 2.0 based power aware equivalence checking using Conformal.

-Debugging PA-FV failures

-Conformal ECO for doing complex functional ECOs.

-Low power synthesis on smaller blocks and subsystems using DC/Genus

-Physical Aware synthesis of small blocks

Education Requirements Bachelors and preferred Masters .

LI-IND*

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