Qualcomm Clock Architecture and RTL Design Engineer in Bangalore, India

Job Description:

Job Id E1956183

Job Title Clock Architecture and RTL Design Engineer

Post Date 09/15/2017

Company-Division Qualcomm Technologies, Inc.


CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area Engineering - Hardware

Location India - Bangalore

Job Overview Job Description :

Architecture and design of clock controllers for SoC. Collate clock requirements from IPs and arrive at clock plan for the chip. Have the ability to work with multiple teams across varied geographical locations. Have sound understanding of chip flow and constraints. Work with PD and synthesis teams to ensure proper constraints and timing closure. Analyze and improve power aspects of clocking. Own the clock spec and guide DV in ensuring proper validation . Work with SW/VI during silicon debug and bringup. Have thorough understanding of various reset schemes and chip reset mechanisms

Mandatory Skills

Verilog / System Verilog RTL coding

High degree of comfort in Unix

Efficient in TCL / Perl scripting

Thorough timing analysis

Ability to debug waveforms , VCS/Novas knowledge is a plus

Good to have skills

Knowledge of DFT

Usage of PrimeTime

Experience of working on Verdi / Similar tools for ECO

FV debug ability

Experience : 2 8 years

Minimum Qualifications Job Description :

Architecture and design of clock controllers for SoC. Collate clock requirements from IPs and arrive at clock plan for the chip. Have the ability to work with multiple teams across varied geographical locations. Have sound understanding of chip flow and constraints. Work with PD and synthesis teams to ensure proper constraints and timing closure. Analyze and improve power aspects of clocking. Own the clock spec and guide DV in ensuring proper validation . Work with SW/VI during silicon debug and bringup. Have thorough understanding of various reset schemes and chip reset mechanisms

Mandatory Skills

Verilog / System Verilog RTL coding

High degree of comfort in Unix

Efficient in TCL / Perl scripting

Thorough timing analysis

Ability to debug waveforms , VCS/Novas knowledge is a plus

Good to have skills

Knowledge of DFT

Usage of PrimeTime

Experience of working on Verdi / Similar tools for ECO

FV debug ability

Experience : 2 8 years

Preferred Qualifications Job Description :

Architecture and design of clock controllers for SoC. Collate clock requirements from IPs and arrive at clock plan for the chip. Have the ability to work with multiple teams across varied geographical locations. Have sound understanding of chip flow and constraints. Work with PD and synthesis teams to ensure proper constraints and timing closure. Analyze and improve power aspects of clocking. Own the clock spec and guide DV in ensuring proper validation . Work with SW/VI during silicon debug and bringup. Have thorough understanding of various reset schemes and chip reset mechanisms

Mandatory Skills

Verilog / System Verilog RTL coding

High degree of comfort in Unix

Efficient in TCL / Perl scripting

Thorough timing analysis

Ability to debug waveforms , VCS/Novas knowledge is a plus

Good to have skills

Knowledge of DFT

Usage of PrimeTime

Experience of working on Verdi / Similar tools for ECO

FV debug ability

Experience : 2 8 years

Education Requirements Bachelors and preferred Masters .

LI-IND*

EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.