Qualcomm ASIC/IP Verification Lead/Architect (DDR PHY Design Verification) in Bangalore, India
Job Id E1957784
Job Title ASIC/IP Verification Lead/Architect (DDR PHY Design Verification)
Post Date 09/14/2017
Company-Division Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Job Area Engineering - Hardware
Location India - Bangalore
Job Overview You will be responsible for understanding the analog-digital partition at system level, develop testplan for functional and circuit performance verification, develop the scalable testbench using the SVTB-UVM, test case development, debugging, coverage model development, coverage closure.
You will be working with analog circuit design team, digital design team, analog modeling, characterization team, SoC integration team to complete the successful core level verification, integration into SoC, post-silicon validation
Minimum Qualifications 5-15 years of experience in digital design & verification.
Test planning, problem solving, debug, adversarial testing.
Strong working knowledge of SystemVerilog Testbench, UVM methodology.
Low Power design concepts, Low Power Verification Methodology.
Verification of high-speed DDR PHY and/or DRAM Controller.
Well versed with JEDEC protocol for LPDDR2/LPDDR3/LPDDR4
Preferred Qualifications Verification of high-speed parallel/serial IO interfaces such as D-PHY, M-PHY, SATA, Display Port, PCIe, USB2.0, USB3.0, HDMI experience is plus.
Mixed signal methodology experience (spice in the leaf, spice in the middle) in addition behavioural modelled mixed signal verification is added advantage.
Experience is analog behavioural modeling using Real Number Modeling, Verilog A is added advantage.
FPGA emulation experience is added advantage.
Education Requirements Required: Bachelor's, Electrical Engineering
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.